1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory device and a related method. In particular, embodiments of the invention relate to a semiconductor memory device comprising a control unit receiving a sensing block selection address signal and a method for operating the semiconductor memory device.
2. Description of Related Art
In a conventional semiconductor memory device, a memory cell array includes a plurality of memory cell array blocks and a plurality of sensing blocks. Each memory cell array block is located between two of the sensing blocks. In addition, each of the memory cell array blocks includes a plurality of memory cells, wherein each memory cell is connected to a word line of a plurality of word lines and a bit line of a plurality of bit line pairs. Each memory cell of the plurality of memory cells includes one capacitor and one transistor.
FIG. 1 illustrates the configuration of a conventional semiconductor memory device. The semiconductor memory device of FIG. 1 comprises a memory cell array 100 including i memory cell array blocks BK1 to BKi and (i+1) sensing blocks SA1, SA12, SA23 . . . SA(i−1)i, SAi (i.e., sensing blocks SA1 to SAi). Memory cell array 100 further comprises a row decoder 110, a column decoder 120, and a control unit 130. Each of memory cell array blocks BK1 to BKi includes a plurality of memory cells MC. Each memory cell MC is connected to a word line of word lines (WL11 to WL1k), (WL21 to WL2k), . . . , (WLi1 to WLik). Each memory cell MC is also connected to a bit line of bit line pairs (BL1, BL1B), (BL2, BL2B), (BL3, BL3B), . . . . That is, each memory cell MC is connected between a word line and a bit line. Each of memory cells MC includes an NMOS transistor N and a capacitor C.
In addition, each of sensing blocks SA1 to SAi includes a plurality of sense amplifying units. For example, sensing block SA1 includes sense amplifying units (SA1-1, . . . ), sensing block SA12 includes sense amplifying units (SA12-1, SA12-2, . . . ), and sensing block SAi includes sense amplifying units (SAi-1, . . . ). Although they are not all illustrated in detail, each of the sense amplifying units of the semiconductor memory device of FIG. 1 are substantially the same. Each sense amplifying unit includes bit line isolation gates ISOG1 and ISOG2, a precharge circuit PRE, a bit line sense amplifier BSA, and a column select gate CSG. Each of bit line isolation gates ISOG1 and ISOG2 includes NMOS transistors N1 and N2. In addition, precharge circuit PRE includes NMOS transistors N3, N4, and N5. Also, bit line sense amplifier BSA includes a PMOS sense amplifier including PMOS transistors P1 and P2 and an NMOS sense amplifier including NMOS transistors N6 and N7. Column select gate CSG includes NMOS transistors N8 and N9.
Functions of blocks of the semiconductor memory device illustrated in FIG. 1 will now be described.
In each of memory cell array blocks BK1 to BKi, data is written to or read from a memory cell MC connected between a selected one of word lines (WL11 to WL1k), . . . , (WLi1 to WLik) and a bit line of a selected pair of the bit line pairs. Row decoder 110 decodes a first row address RA1 to select a word line from the plurality of word lines in response to an active command ACT. Column decoder 120 decodes a column address CA to enable a column select signal on one of a plurality of column select signal lines CSL1 to CSLn in response to a write command WR or a read command RD. Control unit 130 decodes a second row address RA2 specifying one of memory cell array blocks BK1 to BKi to select a memory cell array block in response to active command ACT. In addition, during a precharge operation, control unit 130 enables bit line isolation control signals ISO1 and ISO2 and a precharge control signal CPRE of control signal groups CON1 to CONi for sensing blocks SA1 to SAi, respectively. Also, in response to write command WR during a write operation and in response to a read command RD during a read operation, control unit 130 enables sense amplifier enable signals LA and LAB provided to a sensing block disposed on the left side of the selected memory cell array block and enables sense amplifier enable signals LA and LAB provided to a sensing block disposed on the right side of the selected memory cell array block. For example, during the write or read operation, when memory cell array block BK1 is selected, sense amplifier enable signals LA and LAB of control signal group CON1 for sensing block SA1 and sense amplifier enable signals LA and LAB of control signal group CON12 for sensing block SA12 are enabled to operate all of the bit line sense amplifiers in sensing blocks SA1 and SA12 to amplify respective voltage differences between the bit lines of bit line pairs (BL1, BL1B), (BL2, BL2B), (BL3, BL3B), . . . , in order to amplify a voltage difference between the bit lines of one of those bit line pairs.
In the memory cell array of the conventional semiconductor memory device shown in FIG. 1, when one of the memory cell array blocks is specified by second row address RA2, all of the bit line sense amplifiers of the sensing block disposed on the left side and all of the bit line sense amplifiers of the sensing block disposed on the right side of the specified memory cell array block are enabled to amplify respective voltage differences between bit lines of each of the bit line pairs. Accordingly, the data on each bit line pair of the specified memory cell array block is amplified.
However, as the storage capacity and degree of integration of semiconductor memory devices increase, the distance (i.e., interval) between bit lines decreases, so coupling noise may be generated due to coupling capacitance between adjacent bit lines. In addition, data apparent on the bit lines may be changed by the coupling noise.
Referring to FIG. 1, when a voltage apparent on bit line BL2 transitions to a logic high level and respective voltages apparent on adjacent inverted bit lines BL1B and BL2B each transition to a logic low level, coupling noise is generated due to bit line coupling capacitance. The coupling noise may decrease the voltage level apparent on bit line BL2 and increase the respective voltage levels apparent on inverted bit lines BL1B and BL2B, which may change the data on bit lines BL2, BL1B, and BL2B.
Recently, memory cells having no capacitor have been developed for semiconductor memory devices having a relatively high degree of integration. In a semiconductor memory device having such memory cells, the interval between bit lines is smaller than that in the conventional semiconductor memory device illustrated in FIG. 1. Dynamic memory cells having no capacitor are disclosed in U.S. Patent Publication No. 2005/0068807, U.S. Pat. No. 6,567,330, U.S. Pat. No. 6,882,008, etc.